Nowadays, logic circuits and memory circuits are usually fabricated by different semiconductor factories, and then packaged in same integrated circuits (IC) using certain packaging techniques. Generally, to reduce the size of the IC, three-dimensional packaging technique is employed to finish the packaging process. However, as shown in FIG. 1, during a bonding process for stacking two different IC chips 11 and 12, the upper IC chip 12 is usually deformed due to the high process temperature of the bonding process or cracks due to the high inner stress. Thus, it is difficult to improve the yield rate. Therefore, there is a desire to overcome above problems.